EPM3512AFC256-20 vs EPM3512AFC256-22 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-20 sa pamamagitan ng Altera at EPM3512AFC256-22 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-20 EPM3512AFC256-22
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Typical Usable Gates 10,000 —
Speed Grade -20 (20 ns tPD) -22 (tPD ~22 ns)
Packhaging 256-ball FBGA (Fine-pitch BGA) FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch)
Bilang ng Pin 256 —
Operating Voltage (VCCINT) 3.3 V (3.0 V to 3.6 V) —
I/O Voltage (VCCIO) 2.5 V or 3.3 V (5.0 V tolerant inputs) —
I/O Standards LVTTL, LVCMOS, 2.5 V, 3.3 V, 5.0 V tolerant —
Program Memory Type EEPROM (non-volatile) —
In-System Programmability Yes (JTAG IEEE 1149.1) —
JTAG Support Yes (boundary-scan + ISP) —
Uri ng Pagpapasok Surface Mount Surface Mount (BGA)
Temperature na Operasyon [DATA_NEEDED: operating temperature range] [DATA_NEEDED: operating temperature grade]
Tindminan RoHS [DATA_NEEDED: RoHS compliance status] [DATA_NEEDED: RoHS compliance status]
Level ng MSL [DATA_NEEDED: MSL moisture sensitivity level] —
Configuration Memory Internal EEPROM On-chip EEPROM (non-volatile)
Device Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 208 (typical for FC256 package)
Propagation Delay (tPD) — 22 ns
Supply Voltage VCCINT — 3.3 V
I/O Standards Supported — 2.5 V, 3.3 V, 5.0 V (VCCIO selectable)
In-System Programming — IEEE Std. 1532-compliant ISP via JTAG

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