EPM3512AFC256-21 vs EPM3512AFC256-19 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-21 sa pamamagitan ng Altera at EPM3512AFC256-19 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AFC256-21 | EPM3512AFC256-19 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | NRND |
| Device Family | MAX 3000A | — |
| Logic Elements / Macrocells | 512 macrocells | — |
| Usable Gates | 10,000 | 10000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 87 MHz | 80 MHz |
| Packhaging | FBGA-256 (FineLine BGA) | 256-ball FineLine BGA (FC) |
| Temperature na Operasyon | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Supply Voltage - Core (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (multi-volt I/O) | — |
| Programmable Pins (max) | [DATA_NEEDED: maximum user I/O pin count] | — |
| Programming Interface | JTAG / IEEE Std. 1532 ISP | JTAG (IEEE 1149.1) / ISP (IEEE 1532) |
| Uri ng Memory | Non-volatile EPROM/EEPROM cell array | — |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 3000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 512 |
| Pin-to-Pin Delay (tPD) | — | 7.5 ns |
| Speed Grade | — | -19 |
| User I/O Pins | — | 208 |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Supply Voltage VCCIO | — | 2.5 V or 3.3 V (5.0 V tolerant inputs) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Non-volatile Configuration | — | Yes (EEPROM-based) |