EPM3512AFC256-23 vs EPM3512AFC256-22 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-23 sa pamamagitan ng Altera at EPM3512AFC256-22 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM3512AFC256-23 - MAX 3000A CPLD, 512 Macrocells, 256-BGA | Altera
EPM3512AFC256-23 ObsoletePagsanggunian na paghahambing
| Parametro | EPM3512AFC256-23 | EPM3512AFC256-22 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Logic Array Blocks (LABs) | 16 (32 macrocells each) | 16 |
| Maximum Operating Frequency | 178.6 MHz | — |
| Propagation Delay (tPD) | 5.5 ns | 22 ns |
| Pin-to-Pin Delay | 23 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| User I/O Pins | [DATA_NEEDED: user I/O count for FC256] | — |
| Packhaging | 256-ball FineLine BGA (FC256), 17 mm x 17 mm | FC-256 (FineLine BGA, 256 balls, 1.0 mm pitch) |
| Programming Interface | JTAG (IEEE Std. 1149.1) / ISP | — |
| Process Technology | 0.30 µm CMOS EEPROM | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature grade] |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount (BGA) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 208 (typical for FC256 package) |
| Speed Grade | — | -22 (tPD ~22 ns) |
| Supply Voltage VCCINT | — | 3.3 V |
| I/O Standards Supported | — | 2.5 V, 3.3 V, 5.0 V (VCCIO selectable) |
| In-System Programming | — | IEEE Std. 1532-compliant ISP via JTAG |
| Configuration Memory | — | On-chip EEPROM (non-volatile) |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance status] |