EPM3512AFC256-3N vs EPM3512AFC256-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-3N sa pamamagitan ng Altera at EPM3512AFC256-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AFC256-3N | EPM3512AFC256-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | 10,000 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Maximum Operating Frequency | 116.3 MHz | — |
| Pin-to-Pin Delay (tPD) | 3.5 ns (speed grade -3) | 10 ns |
| Speed Grade | -3 (slowest in family) | — |
| Core Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Supply Voltage (VCCIO) | 2.5 V / 3.3 V / 5.0 V (MultiVolt) | — |
| Packhaging | 256-ball FineLine BGA (FC-256) | 256-pin FBGA |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programming Interface | JTAG (IEEE 1149.1) / IEEE Std. 1532 ISP | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance status] | unknown |
| Maximum I/O Pins | — | 208 |
| Maximum Counter Frequency | — | 87 MHz |
| Supply Voltage (VCCINT) | — | 3.3 V |
| I/O Voltage Tolerance | — | 5-V tolerant |
| Programmable Technology | — | CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532) |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: industrial/commercial operating temperature range] |
| Bilang ng Pin | — | 256 |
| Architecture | — | MAX (Multiple Array matriX) EEPROM-based |