EPM3512AFC256-7 vs EPM3256AFC256-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-7 sa pamamagitan ng Intel at EPM3256AFC256-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-7 EPM3256AFC256-7
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 —
Logic Array Blocks (LABs) 16 16
User I/O Pins 212 —
Usable Gates 10,000 10,000
Pin-to-Pin Logic Delay 7.5 ns 4.5 ns (max)
Counter Frequency (max) 227.3 MHz —
Supply Voltage - Core (VCCINT) 3.0 V to 3.6 V (3.3 V typ.) —
I/O Voltage (VCCIO) 5.0 V / 3.3 V / 2.5 V (MultiVolt) —
Packhaging 256-ball FineLine BGA (FBGA-256) FBGA-256 (FineLine BGA), 256 balls
Programming EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] 0 °C to 70 °C (Commercial)
Uri ng Pagpapasok Surface Mount —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance status]
Configuration Memory Non-volatile EEPROM —
Macro Cells — 256
User I/Os — 161
Counter Frequency — 227.3 MHz (max)
Propagation Delay (tpd) — 10 ns
Core Voltage — 3.3 V
I/O Compatibility — 5.0 V / 3.3 V / 2.5 V (MultiVolt I/O)
Process Technology — CMOS EEPROM, 0.30 µm
In-System Programmability — IEEE Std. 1532-compliant 3.3-V ISP
Boundary-Scan Test — JTAG (IEEE 1149.1)
Speed Grade — -7

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