EPM3512AFC256-7 vs EPM3512AQC20-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-7 sa pamamagitan ng Intel at EPM3512AQC20-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3512AFC256-7 - 512-Macrocell MAX 3000A CPLD, 7.5ns, BGA-256 | Intel
EPM3512AFC256-7 ⚠ Huling Pagbili
Pagsanggunian na paghahambing
| Parametro | EPM3512AFC256-7 | EPM3512AQC20-10 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | NRND |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 16 | 16 |
| User I/O Pins | 212 | 100 |
| Usable Gates | 10,000 | — |
| Pin-to-Pin Logic Delay | 7.5 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage - Core (VCCINT) | 3.0 V to 3.6 V (3.3 V typ.) | — |
| I/O Voltage (VCCIO) | 5.0 V / 3.3 V / 2.5 V (MultiVolt) | — |
| Packhaging | 256-ball FineLine BGA (FBGA-256) | PQFP-240 (QC20 designation per Altera ordering code) |
| Programming | EEPROM, IEEE 1149.1 JTAG ISP (IEEE 1532-compliant) | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Compliant (lead-free PQFP package) |
| Configuration Memory | Non-volatile EEPROM | — |
| Macrocells per LAB | — | 32 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | 116.3 MHz |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | — | IEEE 1149.1 (JTAG) - In-System Programmable |
| Process Technology | — | 0.30 µm EEPROM CMOS |