EPM3512AFC256-7N vs EPM3512AFC256-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AFC256-7N sa pamamagitan ng Altera at EPM3512AFC256-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AFC256-7N EPM3512AFC256-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Product Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 10,000
User I/Os 208 —
Logic Blocks 16 (32 macrocells each) —
Propagation Delay (tPD) 7.5 ns —
Maximum Internal Frequency (fMAX) 116.3 MHz —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
5V Tolerant I/O Yes —
In-System Programmability IEEE Std. 1532 compliant Yes (IEEE Std. 1149.1 JTAG / IEEE Std. 1532)
Programming Interface JTAG (IEEE 1149.1) —
Process Technology CMOS EEPROM, 0.30 um —
Packhaging 256-pin FineLine BGA (FBGA-256), 1.0 mm pitch 256-pin FBGA
Temperature na Operasyon 0 C to 70 C (commercial) —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: RoHS status] unknown
Logic Array Blocks (LABs) — 16
Maximum I/O Pins — 208
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Counter Frequency — 87 MHz
Supply Voltage (VCCINT) — 3.3 V
I/O Voltage Tolerance — 5-V tolerant
Programmable Technology — CMOS EEPROM
Hanay ng Temperature na Operasyon — [DATA_NEEDED: industrial/commercial operating temperature range]
Bilang ng Pin — 256
Architecture — MAX (Multiple Array matriX) EEPROM-based

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