EPM3512AQC20-10 vs EPM3512AQC208-10S Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC20-10 sa pamamagitan ng Altera at EPM3512AQC208-10S sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC20-10 EPM3512AQC208-10S
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Logic Array Blocks (LABs) 16 32 (16 macrocells each)
Macrocells per LAB 32 —
User I/O Pins 100 —
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fCNT) 116.3 MHz —
Supply Voltage VCCINT 5.0 V —
MultiVolt I/O Voltages 5.0 V / 3.3 V / 2.5 V / 1.8 V —
Programming Interface IEEE 1149.1 (JTAG) - In-System Programmable —
Process Technology 0.30 µm EEPROM CMOS EEPROM-based CMOS
Packhaging PQFP-240 (QC20 designation per Altera ordering code) 208-pin FineLine BGA-256
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Tindminan RoHS Compliant (lead-free PQFP package) [DATA_NEEDED: rohs_status]
Usable Gates — 1750
User I/Os — 208
Speed Grade — -10 (tPD1 = 7.5 ns)
Propagation Delay (tPD1) — 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology — CMOS EEPROM
In-System Programmability (ISP) — Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance — Yes (PCI Local Bus Specification Rev 2.2)
Boundary-Scan (JTAG) — Yes (1149.1 compliant)
Program/Erase Endurance — 100 cycles minimum
Logic Family — CMOS

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