EPM3512AQC208-10 vs EPM3512AQC20-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-10 sa pamamagitan ng Altera at EPM3512AQC20-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM3512AQC208-10 | EPM3512AQC20-10 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 3000A | MAX 3000A |
| Usable Gates | 10,000 | — |
| Macrocells | 512 | 512 |
| Logic Array Blocks (LABs) | 32 | 16 |
| User I/Os | 208 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Frequency (fCNT) | 116.3 MHz | 116.3 MHz |
| Supply Voltage (VCCINT) | 3.3 V | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| In-System Programmability | Yes (IEEE Std. 1532) | — |
| JTAG Boundary Scan | Yes (IEEE 1149.1) | — |
| PCI Compliance | PCI Local Bus Spec Rev. 2.2 (-10 speed grade) | — |
| Packhaging | 208-pin PQFP | PQFP-240 (QC20 designation per Altera ordering code) |
| Temperature na Operasyon | 0C to +70 C (commercial) | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS status not in verified data] | Compliant (lead-free PQFP package) |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells per LAB | — | 32 |
| User I/O Pins | — | 100 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage VCCINT | — | 5.0 V |
| MultiVolt I/O Voltages | — | 5.0 V / 3.3 V / 2.5 V / 1.8 V |
| Programming Interface | — | IEEE 1149.1 (JTAG) - In-System Programmable |
| Process Technology | — | 0.30 µm EEPROM CMOS |