EPM3512AQC208-10S vs EPM3512AQC20-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-10S sa pamamagitan ng Altera at EPM3512AQC20-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC208-10S EPM3512AQC20-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 512 512
Usable Gates 1750 —
Logic Array Blocks (LABs) 32 (16 macrocells each) 16
Packhaging 208-pin FineLine BGA-256 PQFP-240 (QC20 designation per Altera ordering code)
User I/Os 208 —
Speed Grade -10 (tPD1 = 7.5 ns) —
Propagation Delay (tPD1) 7.5 ns (pin-to-pin) —
Supply Voltage - VCCINT (internal) 3.3 V —
Supply Voltage - VCCIO (I/O) 2.5 V, 3.3 V, or 5.0 V (MultiVolt) —
Programming Technology CMOS EEPROM —
In-System Programmability (ISP) Yes (IEEE Std. 1149.1 JTAG) —
PCI Compliance Yes (PCI Local Bus Specification Rev 2.2) —
Temperature na Operasyon 0C to +70C (commercial) 0C to +70C (commercial)
Boundary-Scan (JTAG) Yes (1149.1 compliant) —
Program/Erase Endurance 100 cycles minimum —
Logic Family CMOS —
Process Technology EEPROM-based CMOS 0.30 µm EEPROM CMOS
Tindminan RoHS [DATA_NEEDED: rohs_status] Compliant (lead-free PQFP package)
Macrocells per LAB — 32
User I/O Pins — 100
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fCNT) — 116.3 MHz
Supply Voltage VCCINT — 5.0 V
MultiVolt I/O Voltages — 5.0 V / 3.3 V / 2.5 V / 1.8 V
Programming Interface — IEEE 1149.1 (JTAG) - In-System Programmable

Mga Datasheets at Resources

Tingnan ang Lahat ng mga Produkto Lumikha ng BOM Hilingin ang Kita