EPM3512AQC208-7 vs EPM3512AQC208-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-7 sa pamamagitan ng Intel at EPM3512AQC208-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Intel
EPM3512AQC208-7 - MAX 3000A CPLD, 512 Macrocells, 7.5ns, 208-PQFP | Intel
EPM3512AQC208-7 NrndPagsanggunian na paghahambing
| Parametro | EPM3512AQC208-7 | EPM3512AQC208-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 3000A | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 512 | 512 |
| Usable Gates | 10,000 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Counter Frequency (fCNT) | 116.3 MHz | — |
| User I/Os | 172 | — |
| Logic Elements / LEs | N/A (CPLD macrocell architecture) | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Standards Supported | 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) | — |
| Packhaging | 208-Pin PQFP (FQFP, gull-wing) | PQFP-208 (QC) |
| Temperature na Operasyon | 0 C to +70 C (commercial) | — |
| Programming | In-System Programmable via JTAG (IEEE Std. 1532) | — |
| Process Technology | CMOS EEPROM, 0.30 um | 0.30 µm EEPROM |
| Tindminan RoHS | Compliant | Non-compliant (legacy PQFP) |
| Lead-Free | Yes | No (SnPb lead finish) |
| User I/O Pins | — | 172 |
| Logic Array Blocks (LABs) | — | 16 |
| Speed Grade | — | -2 |
| Supply Voltage (Core) | — | 3.3 V |
| Output Drive Voltage | — | 2.5 V / 3.3 V programmable |
| Input Voltage Tolerance | — | 2.5 V / 3.3 V / 5.0 V |
| Program/Erase Endurance | — | 100 cycles (typical) |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| User I/O Banks | — | 4 |
| Hanay ng Temperature na Operasyon | — | Commercial (0C to +70C) |
| Uri ng Pagpapasok | — | Surface Mount |
| Security Bit | — | Yes (programmable) |