EPM3512AQC208-7 vs EPM3512AQC208-3N Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQC208-7 sa pamamagitan ng Intel at EPM3512AQC208-3N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQC208-7 EPM3512AQC208-3N
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 512 512
Usable Gates 10,000 —
Propagation Delay (tPD) 7.5 ns —
Counter Frequency (fCNT) 116.3 MHz —
User I/Os 172 —
Logic Elements / LEs N/A (CPLD macrocell architecture) —
Supply Voltage (VCCINT) 3.3 V —
I/O Standards Supported 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O) —
Packhaging 208-Pin PQFP (FQFP, gull-wing) PQFP-208
Temperature na Operasyon 0 C to +70 C (commercial) 0C to +70C (commercial)
Programming In-System Programmable via JTAG (IEEE Std. 1532) —
Process Technology CMOS EEPROM, 0.30 um —
Tindminan RoHS Compliant [DATA_NEEDED: not stated in retrieved snippets]
Lead-Free Yes —
User I/O Pins — 172
Logic Array Blocks (LABs) — 16
Macrocells per LAB — 32
Pin-to-Pin Logic Delay — 3 ns (speed grade -3)
Global Clock Setup Time — [DATA_NEEDED: actual tSU at 3 ns grade]
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V (MultiVolt 1.8 V / 2.5 V / 3.3 V / 5.0 V tolerant)
Uri ng Pagpapasok — Surface Mount
Programming Technology — EEPROM (non-volatile, in-system programmable)
JTAG / Boundary Scan — IEEE 1149.1 compliant
ISP Compliance — IEEE Std. 1532
Lead-Free / Halogen-Free — [DATA_NEEDED]

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