EPM3512AQI208-10N vs EPM3512AQI208-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQI208-10N sa pamamagitan ng Intel at EPM3512AQI208-7 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQI208-10N EPM3512AQI208-7
Brand Intel Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Logic Family CMOS EEPROM-based —
Macro Cells 512 512
Logic Array Blocks (LABs) 12 16
User I/Os 172 (max), 208-pin package —
Propagation Delay (tPD) 10 ns —
Volte ng Pagbibigay 3.3 V —
I/O Standards MultiVolt (2.5 V / 3.3 V / 5 V tolerant) —
Package Type PQFP-208 (FINE LINE BGA-style 256-pin land) —
Pins 256 (package), 208 used —
Temperature na Operasyon 0C to 70C -40C to +85C (industrial)
Uri ng Pagpapasok Surface Mount Surface Mount
Programming Interface JTAG (IEEE 1149.1) / ISP (IEEE 1532) —
Compliance RoHS status unknown from data —
Boundary Scan Built-in BST (IEEE 1149.1) —
Configuration Memory On-chip EEPROM, non-volatile —
Usable Gates — 10,000
Maximum Operating Frequency — 116.3 MHz
Speed Grade — -7
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: tPD in ns]
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 2.5 V / 3.3 V / 5.0 V
Programmability — Non-volatile, in-system programmable (IEEE Std. 1532)
JTAG Support — Yes (IEEE 1149.1 boundary scan + ISP)
User I/O Pins — [DATA_NEEDED: user I/O count for PQFP-208]
Packhaging — 208-pin PQFP
Lead-Free / RoHS — Compliant per Altera product page

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