EPM3512AQI208-7 vs EPM3512AQC208-7 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM3512AQI208-7 sa pamamagitan ng Altera at EPM3512AQC208-7 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM3512AQI208-7 EPM3512AQC208-7
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND NRND
Family MAX 3000A MAX 3000A
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Usable Gates 10,000 10,000
Macro Cells 512 —
Logic Array Blocks (LABs) 16 —
Maximum Operating Frequency 116.3 MHz —
Speed Grade -7 —
Pin-to-Pin Delay (tPD) [DATA_NEEDED: tPD in ns] —
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 2.5 V / 3.3 V / 5.0 V —
Programmability Non-volatile, in-system programmable (IEEE Std. 1532) —
JTAG Support Yes (IEEE 1149.1 boundary scan + ISP) —
User I/O Pins [DATA_NEEDED: user I/O count for PQFP-208] —
Packhaging 208-pin PQFP 208-Pin PQFP (FQFP, gull-wing)
Uri ng Pagpapasok Surface Mount —
Temperature na Operasyon -40C to +85C (industrial) 0 C to +70 C (commercial)
Lead-Free / RoHS Compliant per Altera product page —
Macrocells — 512
Propagation Delay (tPD) — 7.5 ns
Counter Frequency (fCNT) — 116.3 MHz
User I/Os — 172
Logic Elements / LEs — N/A (CPLD macrocell architecture)
Supply Voltage (VCCINT) — 3.3 V
I/O Standards Supported — 5.0 V, 3.3 V, 2.5 V (MultiVolt I/O)
Programming — In-System Programmable via JTAG (IEEE Std. 1532)
Process Technology — CMOS EEPROM, 0.30 um
Tindminan RoHS — Compliant
Lead-Free — Yes

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