EPM5016LC-17 vs EPM5016DI-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016LC-17 sa pamamagitan ng Altera at EPM5016DI-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016LC-17 | EPM5016DI-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Technology | CMOS, UV-erasable | CMOS EPROM |
| Macrocells | 16 | 16 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | 1 |
| Propagation Delay (tPD) | 17 ns | 20 ns |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | — |
| Packhaging | Windowed Ceramic DIP (LC) | 20-pin Ceramic DIP (DI), windowed |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | [DATA_NEEDED: VCC nominal] |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Logic Compatibility | TTL/CMOS | — |
| Device Type | — | EPLD (UV-erasable CMOS) |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Total Inputs | — | 16 |
| Configurable I/O Pins | — | 8 |
| Product Terms per Output | — | 8 |
| Output Functions per Macrocell | — | 8 |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| Speed Grade | — | -20 (20 ns tPD) |