EPM5016LC-17 vs EPM5032LC-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5016LC-17 sa pamamagitan ng Altera at EPM5032LC-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5016LC-17 | EPM5032LC-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 EPLD |
| Technology | CMOS, UV-erasable | CMOS EPROM, 1.0 um process |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 17 ns | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | PAL-type AND/OR with PIA |
| Packhaging | Windowed Ceramic DIP (LC) | JLCC-28 (windowed ceramic) |
| Volte ng Pagbibigay | [DATA_NEEDED: VCC range] | — |
| Temperature na Operasyon | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb, ceramic-windowed package) |
| Logic Compatibility | TTL/CMOS | — |
| Usable Gates | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |