EPM5016LC-17 vs EPM5032LC-15 比較
詳細並排比較 EPM5016LC-17 由 Altera 與 EPM5032LC-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5016LC-17 | EPM5032LC-15 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 EPLD |
| Technology | CMOS, UV-erasable | CMOS EPROM, 1.0 um process |
| Macrocells | 16 | 32 |
| Product Terms | 160 | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 8 | — |
| Total Input Pins | 16 | — |
| Outputs | 8 | — |
| External Clock Inputs | 1 | — |
| Propagation Delay (tPD) | 17 ns | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | PAL-type AND/OR with PIA |
| 封裝 | Windowed Ceramic DIP (LC) | JLCC-28 (windowed ceramic) |
| 供應電壓 | [DATA_NEEDED: VCC range] | — |
| 工作溫度 | [DATA_NEEDED: temperature grade] | 0C to +70C (commercial) |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | Non-compliant (contains Pb, ceramic-windowed package) |
| Logic Compatibility | TTL/CMOS | — |
| Usable Gates | — | 600 |
| Logic Array Blocks (LABs) | — | 4 |
| Bidirectional I/O Pins | — | 16 |
| Maximum Operating Frequency | — | 83.3 MHz |
| Pin-to-Pin Delay (tPD) | — | 15 ns |
| Supply Voltage (VCC) | — | 5 V (4.75 V to 5.25 V) |
| Programmability | — | UV-Erasable / OTP |