EPM5032DC20 vs EPM5016DC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032DC20 sa pamamagitan ng Altera at EPM5016DC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032DC20 | EPM5016DC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-erasable PLD (CPLD class) | — |
| Macrocells | 32 | 16 |
| Usable Gates | 600 | — |
| Propagation Delay (tPD) | 20 ns | 20 ns |
| Maximum Frequency (Fmax) | 71.4 MHz | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | — |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 16 (bidirectional) | 8 |
| Total Inputs (max) | 24 | — |
| Output Macrocells | 16 | — |
| Clock Inputs | 1 (global) | — |
| Architecture | PAL-type with Programmable Interconnect Array (PIA) | PAL-type macrocell with Programmable Interconnect Array (PIA) |
| Process Technology | CMOS | CMOS, UV-erasable |
| Packhaging | 20-pin Ceramic DIP (DC) with UV window | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| Uri ng Pagpapasok | Through-Hole (DIP) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Family | — | MAX 5000 |
| Device Type | — | EPLD (UV-Erasable Programmable Logic Device) |
| Product Terms | — | 160 |
| Maksimum na Taktiko ng Oras | — | 62.5 MHz |
| Maximum Supply Voltage | — | 5.25 V |
| Nominal Supply Voltage | — | 5.0 V |
| Package Type | — | 20-pin Ceramic DIP (Cerdip) with UV window |
| Package Suffix Code | — | DC = Ceramic DIP, Commercial |
| Speed Grade | — | -20 = 20 ns tPD |
| Programming Method | — | UV erase + EPROM-style programming via Altera programming hardware |