EPM5032JC25 vs EPM5032LC-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5032JC25 sa pamamagitan ng Altera at EPM5032LC-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5032JC25 | EPM5032LC-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Inputs to Array | 24 | — |
| Bilang ng Outputs | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | — |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| Volte ng Pagbibigay | 5 V (TTL-level I/O) | — |
| Packhaging | 28-pin PLCC (JC) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Usable Gates | — | 600 gates |
| Macrocells | — | 32 |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| Temperature na Operasyon | — | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Level ng MSL | — | [DATA_NEEDED: MSL] |