EPM5032JC25 vs EPM5032LC-20 比較
詳細並排比較 EPM5032JC25 由 Altera 與 EPM5032LC-20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5032JC25 | EPM5032LC-20 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device | EPM5032 | — |
| Logic Elements | 32 macrocells | — |
| Propagation Delay (tPD) | 25 ns | 20 ns |
| Maximum Internal Frequency | 62.5 MHz | — |
| Product Terms | 320 | — |
| Flip-Flops | 32 | — |
| Dedicated Inputs | 7 | 7 |
| Bidirectional I/O Pins | 16 | 16 |
| Total Inputs to Array | 24 | — |
| 輸出數量 | 16 | — |
| Architecture | PAL-type macrocells with global Programmable Interconnect Array (PIA) | — |
| Technology | CMOS EPROM, UV-erasable (windowed) / OTP | — |
| 供應電壓 | 5 V (TTL-level I/O) | — |
| 封裝 | 28-pin PLCC (JC) | LCC-28 (Plastic Leaded Chip Carrier, J-lead) |
| 安裝類型 | Surface Mount | Surface Mount |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 5000 |
| Product Type | — | EPLD / CPLD (One-Time Programmable / UV-Erasable) |
| Usable Gates | — | 600 gates |
| Macrocells | — | 32 |
| Logic Blocks (LABs) | — | 1 |
| Speed Grade | — | -20 (20 ns pin-to-pin) |
| Maximum Frequency | — | 71.4 MHz |
| Supply Voltage (VCC) | — | 5 V ±5% |
| 工作溫度 | — | 0 °C to +70 °C (commercial; -55 °C to +125 °C military per /883B variants) |
| Total Inputs | — | 24 |
| Output Functions | — | 16 |
| Product Terms per Output | — | 16 |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| MSL 等級 | — | [DATA_NEEDED: MSL] |