EPM5064JC1 vs EPM5064JC Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064JC1 sa pamamagitan ng Altera at EPM5064JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064JC1 EPM5064JC
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 MAX 5000
Device Type CPLD / EPLD (Erasable PLD) EPLD (Erasable PLD)
Macrocells 64 64
Logic Array Blocks (LABs) 4 —
Usable Gates 1.25K 1,250 (approx.)
Maximum Operating Frequency (fCNT) 62.5 MHz —
External Clock Input (max) 50 MHz —
I/O Pins 28 —
Dedicated Inputs 7 —
Total Inputs 36 (28 I/O + 7 dedicated + 1 clock) —
Operating Voltage (VCC) 5 V —
Program Type EPROM (one-time programmable, UV-erasable) —
Process Technology CMOS —
Packhaging 44-pin PLCC (J-Lead) 68-pin PLCC (JEDEC)
Operating Temperature (JC suffix) 0°C to +70°C (commercial) —
Supply Current (ICC) [DATA_NEEDED: ICC maximum] —
Tindminan RoHS unknown [DATA_NEEDED: RoHS compliance]
Lead-Free Status unknown —
Logic Array Inputs — 36
Logic Array Outputs — 64
Uri ng Pagpapasok — Surface Mount (socketed)
Supply Voltage (VCC) — 5 V (typical, 4.75 V - 5.25 V range)
I/O Logic Level — TTL / CMOS compatible
Configuration Memory — EPROM (UV-erasable window or OTP)
Temperature na Operasyon — [DATA_NEEDED: operating temperature grade]
Pin-to-Pin Delay (tPD) — [DATA_NEEDED: specific tPD grade value]
Maximum Frequency (fMAX) — [DATA_NEEDED: fCNT grade value]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Programming Tool — Altera MAX+PLUS II / Quartus II (legacy device support)

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