EPM5064JC1 vs EPM5064JC 比較
詳細並排比較 EPM5064JC1 由 Altera 與 EPM5064JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5064JC1 | EPM5064JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD / EPLD (Erasable PLD) | EPLD (Erasable PLD) |
| Macrocells | 64 | 64 |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 1.25K | 1,250 (approx.) |
| Maximum Operating Frequency (fCNT) | 62.5 MHz | — |
| External Clock Input (max) | 50 MHz | — |
| I/O Pins | 28 | — |
| Dedicated Inputs | 7 | — |
| Total Inputs | 36 (28 I/O + 7 dedicated + 1 clock) | — |
| Operating Voltage (VCC) | 5 V | — |
| Program Type | EPROM (one-time programmable, UV-erasable) | — |
| Process Technology | CMOS | — |
| 封裝 | 44-pin PLCC (J-Lead) | 68-pin PLCC (JEDEC) |
| Operating Temperature (JC suffix) | 0°C to +70°C (commercial) | — |
| Supply Current (ICC) | [DATA_NEEDED: ICC maximum] | — |
| RoHS 狀態 | unknown | [DATA_NEEDED: RoHS compliance] |
| Lead-Free Status | unknown | — |
| Logic Array Inputs | — | 36 |
| Logic Array Outputs | — | 64 |
| 安裝類型 | — | Surface Mount (socketed) |
| Supply Voltage (VCC) | — | 5 V (typical, 4.75 V - 5.25 V range) |
| I/O Logic Level | — | TTL / CMOS compatible |
| Configuration Memory | — | EPROM (UV-erasable window or OTP) |
| 工作溫度 | — | [DATA_NEEDED: operating temperature grade] |
| Pin-to-Pin Delay (tPD) | — | [DATA_NEEDED: specific tPD grade value] |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: fCNT grade value] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL 等級 | — | [DATA_NEEDED: MSL rating] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus II (legacy device support) |