EPM5064LI vs EPM5064LC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5064LI sa pamamagitan ng Altera at EPM5064LC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5064LI EPM5064LC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 64 64
Logic Array Blocks (LABs) 4 4
Number of Terminals 44 —
Package Code QCCJ (PLCC-44, J-bend) —
Package Shape Square —
Configuration Memory UV-Erasable / OTP (EPROM-based) —
Supply Voltage (VCC) 4.5 V to 5.5 V 4.75 V to 5.25 V (5 V nominal)
Operating Temperature Grade Industrial —
Maksimum na Taktiko ng Oras 33.3 MHz —
Propagation Delay (tPD) 55 ns (typical) 45 ns
I/O Pins 28 bidirectional —
Dedicated Inputs 7 —
Total User Inputs 36 —
Process Technology 1-micron EPIC CMOS CMOS, OTP EPROM (UV-erasable base)
Latch-up Immunity 500 mA typical at 125 C —
Uri ng Pagpapasok Surface Mount Surface Mount
Tindminan RoHS [DATA_NEEDED: confirm RoHS status - legacy Altera part] [DATA_NEEDED: not specified in source]
Device Family — MAX 5000
Product Type — CPLD (Complex Programmable Logic Device)
Logic Elements per LAB — 16
Number of Inputs — 36 (7 dedicated + 28 I/O)
Number of I/O Pins — 28
Number of Flip-Flops — 28
Maximum Internal Frequency — 40 MHz
Programmable Polarity — Yes
Programmable Output Enable — Yes, per macrocell
Temperature na Operasyon — -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
Packhaging — PLCC-44 (J-Lead, plastic)
Programming Method — Altera byte-wide / JTAG programmer

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