EPM5128GC-2 vs EPM5064LC-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128GC-2 sa pamamagitan ng Altera at EPM5064LC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5128GC-2 EPM5064LC-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 5000 —
Logic Elements / Gates 2,500 usable gates —
Macrocells 128 64
Number of Usable Gates 2,500 —
Maximum Operating Frequency 50 MHz —
Propagation Delay (tPD) Approx. 25 ns (typical, -2 speed grade) 45 ns
Supply Voltage (VCC) 5 V (nominal) 4.75 V to 5.25 V (5 V nominal)
Package Type 68-pin PGA (Pin Grid Array) —
Package Code (per Partstack) WPGA —
Number of Terminals 68 —
Programming Technology UV-erasable EPROM —
Temperature na Operasyon 0C to +70C (commercial) -40 C to +85 C (commercial LC grade) [DATA_NEEDED: explicit min/max in source]
Grade (per Partstack) COMMERCIAL —
Terminal Form PIN/PEG —
Configuration Memory Non-volatile, one-time programmable (erasable via UV) —
Device Family — MAX 5000
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 4
Logic Elements per LAB — 16
Number of Inputs — 36 (7 dedicated + 28 I/O)
Number of I/O Pins — 28
Number of Flip-Flops — 28
Maximum Internal Frequency — 40 MHz
Process Technology — CMOS, OTP EPROM (UV-erasable base)
Programmable Polarity — Yes
Programmable Output Enable — Yes, per macrocell
Packhaging — PLCC-44 (J-Lead, plastic)
Uri ng Pagpapasok — Surface Mount
Tindminan RoHS — [DATA_NEEDED: not specified in source]
Programming Method — Altera byte-wide / JTAG programmer

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