EPM5128JC vs EPM5128GM883B Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128JC sa pamamagitan ng Altera at EPM5128GM883B sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128JC | EPM5128GM883B |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Product Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | UV EPLD (Erasable Programmable Logic Device) |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 35 ns | — |
| Logic Elements | Programmable AND/OR/XOR array | — |
| Supply Voltage (VCC) | 5 V (typical) | — |
| Bilang ng Pins | 68 | — |
| Package Type | PLCC-68 (JLCC) ceramic, J-leaded | — |
| Dedicated Inputs | 8 | 7 |
| User I/O Pins | [DATA_NEEDED: user I/O pin count] | 52 |
| Configuration Memory | UV-erasable EPROM (windowed package) | UV-erasable EPROM |
| Programming Interface | Altera MAX+PLUS II / A+PLUS / legacy programmer | — |
| Temperature na Operasyon | Commercial 0C to +70C | -55C to +125C (military) |
| Uri ng Pagpapasok | Surface Mount (PLCC socket or solder) | — |
| Boundary Scan | JTAG IEEE 1149.1 (family feature) | — |
| Process Technology | CMOS EPROM | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status - legacy part] | — |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Family | — | MAX 5000 |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Propagation Delay (tpd) | — | 55 ns |
| External Clock Inputs | — | 1 |
| Technology | — | CMOS |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Packhaging | — | PGA-883 (ceramic pin grid array) |
| Qualification | — | MIL-STD-883 Class B (suffix 883B) |
| Program/Erase Method | — | UV-erasable |