EPM5128LC2 vs EPM5128JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5128LC2 sa pamamagitan ng Altera at EPM5128JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5128LC2 | EPM5128JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Huling Pagbili | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | UV-Erasable Programmable Logic Device (PLD) |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 dedicated | — |
| Propagation Delay (tPD) | 45 ns | 45 ns (max) |
| Supply Voltage (VCC) | 5 V | — |
| Process Technology | CMOS EPROM | CMOS |
| Configuration Memory | On-chip EPROM (non-volatile) | — |
| Boundary Scan | JTAG / IEEE 1149.1 | — |
| Temperature na Operasyon | -40 C to +85 C (extended commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | PGA (Pin Grid Array, ceramic) | 68-pin CQCC (Ceramic Quad Flat Pack), windowed |
| Uri ng Pagpapasok | Through-Hole / Socketed | Surface Mount |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic windowed package contains lead-bearing solder) |
| Dedicated Inputs | — | 7 |
| Maximum Counter Frequency (fCNT) | — | 50 MHz |
| Input Setup Time (tSU) | — | 7.5 ns |
| Output Drive Current (IOH/IOL) | — | 12 mA DC |
| Volte ng Pagbibigay | — | 5 V (nominal) |
| Program/Erase Method | — | UV (ceramic window) |
| Erase/Program Cycles | — | [DATA_NEEDED: minimum erase/program cycles] |
| Logic Family | — | TTL-compatible I/O |