EPM5130JC-1 vs EPM5128JC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130JC-1 sa pamamagitan ng Altera at EPM5128JC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130JC-1 | EPM5128JC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | — |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Dedicated Inputs | 19 | 8 |
| I/O Pins | 80 | — |
| Packhaging | 84-pin PLCC (J-lead) | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount (PLCC socket or solder) |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS EPROM |
| Temperature na Operasyon | 0C to +70C (commercial) | Commercial 0C to +70C |
| External Clock Pins | 1 global clock | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - legacy part] |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| Bilang ng Pins | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |