EPM5130JC-1 vs EPM5128JC 比較
詳細並排比較 EPM5130JC-1 由 Altera 與 EPM5128JC 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5130JC-1 | EPM5128JC |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Family | MAX 5000 | — |
| Usable Gates | 2,500 gates | — |
| Macrocells | 128 | — |
| Logic Array Blocks (LABs) | 8 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tPD) | 40 ns | 35 ns |
| Supply Voltage (VCC) | 5 V | 5 V (typical) |
| Dedicated Inputs | 19 | 8 |
| I/O Pins | 80 | — |
| 封裝 | 84-pin PLCC (J-lead) | — |
| 安裝類型 | Surface Mount | Surface Mount (PLCC socket or solder) |
| Programming Technology | UV-erasable EPROM (quartz window) | — |
| Process Technology | CMOS | CMOS EPROM |
| 工作溫度 | 0C to +70C (commercial) | Commercial 0C to +70C |
| External Clock Pins | 1 global clock | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status - legacy part] |
| Product Family | — | MAX 5000 |
| Device Type | — | EPLD / CPLD |
| Macrocell Count | — | 128 |
| Logic Elements | — | Programmable AND/OR/XOR array |
| 腳位數 | — | 68 |
| Package Type | — | PLCC-68 (JLCC) ceramic, J-leaded |
| User I/O Pins | — | [DATA_NEEDED: user I/O pin count] |
| Configuration Memory | — | UV-erasable EPROM (windowed package) |
| Programming Interface | — | Altera MAX+PLUS II / A+PLUS / legacy programmer |
| Boundary Scan | — | JTAG IEEE 1149.1 (family feature) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |