EPM5130LC vs EPM5128LC2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130LC sa pamamagitan ng Altera at EPM5128LC2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130LC | EPM5128LC2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Series | MAX 5000 | — |
| Family | MAX 5000 (EPM51xx) | MAX 5000 |
| Macrocells | 128 | 128 |
| Logic Array Blocks (LABs) | 8 | 8 |
| User I/O Pins | 48 | — |
| Total Inputs (Dedicated + I/O) | 68 | — |
| Dedicated Inputs | 19 | — |
| Propagation Delay (tPD) | 55 ns | 45 ns |
| Maximum Internal Clock Frequency | 50 MHz | — |
| Global Clock Inputs | 1 | 1 dedicated |
| Configuration Technology | UV-Erasable / OTP EPROM | — |
| Process Technology | CMOS (0.7 um EPROM) | CMOS EPROM |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | 5 V |
| I/O Standard | TTL-compatible | — |
| Packhaging | JLCC-68 (J-Lead Ceramic Chip Carrier) | PGA (Pin Grid Array, ceramic) |
| Temperature na Operasyon | [DATA_NEEDED: commercial/industrial/military grade] | -40 C to +85 C (extended commercial) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole / Socketed |
| Tindminan RoHS | Non-compliant (ceramic JLCC, contains lead) | [DATA_NEEDED: RoHS status] |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | On-chip EPROM (non-volatile) |
| Boundary Scan | — | JTAG / IEEE 1149.1 |