EPM5130WC-2 vs EPM5130LC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5130WC-2 sa pamamagitan ng Altera at EPM5130LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5130WC-2 | EPM5130LC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 | — |
| Product Type | UV-Erasable PLD (CPLD) | — |
| Macrocell Count | 128 | — |
| Propagation Delay (tPD) | 45 ns | 55 ns |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | 4.5 V to 5.5 V |
| Temperature na Operasyon | 0 °C to 70 °C (Commercial) | [DATA_NEEDED: commercial/industrial/military grade] |
| Process Technology | CMOS | CMOS (0.7 um EPROM) |
| Dedicated Inputs | 19 | 19 |
| User I/O Lines | 48 | — |
| Total Inputs (I/O + dedicated) | 68 | — |
| Package Type | 100-terminal Ceramic CQFP (R-CQFP-G100), windowed, gull-wing | — |
| Terminal Pitch | 0.650 mm | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | UV-erasable CMOS EEPROM cells | — |
| Speed Grade | -2 (45 ns) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic JLCC, contains lead) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Logic Elements | AND/OR array with programmable macrocell register | — |
| Series | — | MAX 5000 |
| Family | — | MAX 5000 (EPM51xx) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| User I/O Pins | — | 48 |
| Total Inputs (Dedicated + I/O) | — | 68 |
| Maximum Internal Clock Frequency | — | 50 MHz |
| Global Clock Inputs | — | 1 |
| Configuration Technology | — | UV-Erasable / OTP EPROM |
| I/O Standard | — | TTL-compatible |
| Packhaging | — | JLCC-68 (J-Lead Ceramic Chip Carrier) |