EPM5192-1LC vs EPM5128LC2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192-1LC sa pamamagitan ng Altera at EPM5128LC2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192-1LC | EPM5128LC2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Huling Pagbili |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 3,750 | — |
| Macrocells | 192 | 128 |
| Logic Array Blocks (LABs) | 4 | 8 |
| User I/O Pins | 64 | — |
| Maximum Operating Frequency | 62.5 MHz | — |
| Propagation Delay (tpd) | [DATA_NEEDED: -1 speed grade tpd in ns] | — |
| Volte ng Pagbibigay | 5 V | — |
| Process Technology | UV EPROM, erasable windowless | CMOS EPROM |
| Programmable Interconnect | PIA (Programmable Interconnect Array) | — |
| JTAG Boundary Scan | IEEE 1149.1 compliant | — |
| Packhaging | 64-pin Ceramic J-Lead Chip Carrier (LC) | PGA (Pin Grid Array, ceramic) |
| Uri ng Pagpapasok | Surface Mount | Through-Hole / Socketed |
| Temperature na Operasyon | 0C to +70C (commercial) | -40 C to +85 C (extended commercial) |
| Tindminan RoHS | Non-compliant (ceramic windowless package, lead-bearing termination) | [DATA_NEEDED: RoHS status] |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Global Clock Inputs | — | 1 dedicated |
| Propagation Delay (tPD) | — | 45 ns |
| Supply Voltage (VCC) | — | 5 V |
| Configuration Memory | — | On-chip EPROM (non-volatile) |
| Boundary Scan | — | JTAG / IEEE 1149.1 |