EPM5192AGC84-15 vs EPM5192AJC84-20 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AGC84-15 sa pamamagitan ng Altera at EPM5192AJC84-20 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM5192AJC84-20 - 192-Macrocell UV PLD, 33ns, 84-Pin J-Lead | Altera
EPM5192AJC84-20 ObsoletePagsanggunian na paghahambing
| Parametro | EPM5192AGC84-15 | EPM5192AJC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | UV-Erasable/OTP Complex PLD | UV-erasable/OTP Complex PLD (CPLD) |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 15 ns | — |
| Maximum Internal Clock Frequency | 83.3 MHz | — |
| Supply Voltage (VCC) | 4.5 V to 5.5 V | — |
| Process Technology | CMOS | CMOS, UV-erasable EEPROM |
| Programmable Element | UV-Erasable EPROM cell | — |
| Packhaging | 84-pin Ceramic PGA (Pin Grid Array) | 84-pin PLCC J-Lead (WQCCJ, J84) |
| Uri ng Pagpapasok | Through-Hole | Surface Mount (J-Lead) |
| Temperature na Operasyon | Commercial (0C to +70C) - [DATA_NEEDED: military/industrial temp grade range] | — |
| Tindminan RoHS | [DATA_NEEDED: not declared in web data; ceramic PGA with UV window typically non-RoHS] | [DATA_NEEDED: RoHS status] |
| Propagation Delay (tpd) | — | 33 ns (speed grade -20) |
| Maksimum na Taktiko ng Oras | — | 66.7 MHz |
| Supply Voltage (Vcc) | — | 4.75 V to 5.25 V |
| User I/O Lines | — | 64 |
| Operating Temperature Grade | — | Commercial |
| Level ng MSL | — | [DATA_NEEDED: MSL level] |
| Programming Tool | — | Altera MAX+PLUS II / Quartus (legacy) |
| Lead-Free / Halogen-Free | — | [DATA_NEEDED: lead-free status] |