EPM5192AJC-15 vs EPM5192GC1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192AJC-15 sa pamamagitan ng Intel at EPM5192GC1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192AJC-15 | EPM5192GC1 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | — |
| Logic Capacity | 100% connectivity, sum-of-products PLA architecture | — |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Supply Voltage (VCC) | 5 V (4.75 V to 5.25 V) | 5 V |
| Temperature na Operasyon | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| Packhaging | 84-pin PLCC (J-lead, ceramic, non-windowed) | — |
| Uri ng Pagpapasok | Surface Mount | Through-hole (PGA) |
| Programmability | UV-erasable (windowed variant) / One-Time-Programmable | — |
| Toolchain | MAX+PLUS II | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Bilang ng Pin | 84 | — |
| User I/O Pins | [DATA_NEEDED: user I/O count] | — |
| Speed Grades Available | -15, -20, -25 (this part: -15) | — |
| Configuration Memory | EPROM (UV-erasable) | — |
| Macro Cells | — | 192 |
| Usable Gates | — | 3,750 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Programming Technology | — | UV-Erasable / OTP EPROM |
| Package Type | — | Ceramic PGA (Pin Grid Array) |
| Logic Elements | — | 192 macrocells with AND/OR array |
| Process Technology | — | EPROM-based CMOS |
| Propagation Delay | — | [DATA_NEEDED: tpd specification] |
| Bilang ng Pins | — | [DATA_NEEDED: pin count for GC1 PGA package] |
| Development Tool | — | Altera MAX+PLUS II |