EPM5192GC1 vs EPM5192JC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GC1 sa pamamagitan ng Altera at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GC1 | EPM5192JC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD - Complex Programmable Logic Device |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | 3750 |
| Maximum Operating Frequency | 62.5 MHz | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Programming Technology | UV-Erasable / OTP EPROM | — |
| Package Type | Ceramic PGA (Pin Grid Array) | 84-pin Ceramic Quad Flat Pack (CQFP), windowed |
| Logic Elements | 192 macrocells with AND/OR array | — |
| Process Technology | EPROM-based CMOS | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | 0 C to +70 C (commercial) |
| Propagation Delay | [DATA_NEEDED: tpd specification] | — |
| Bilang ng Pins | [DATA_NEEDED: pin count for GC1 PGA package] | — |
| Uri ng Pagpapasok | Through-hole (PGA) | — |
| Tindminan RoHS | unknown | — |
| Development Tool | Altera MAX+PLUS II | — |
| Technology | — | CMOS, UV-Erasable / OTP |
| Macrocells | — | 192 |
| Propagation Delay (tPD) | — | 40 ns (speed grade -1) |
| Maximum Internal Frequency (fMAX) | — | 62.5 MHz |
| User I/O Pins | — | 84 |
| JEDEC Package Code | — | S-CQCC-J84 |
| Configuration Memory | — | UV-EPROM (erasable under UV lamp) |
| Programming Interface | — | Altera MAX programming interface (parallel, pre-JTAG for this family) |
| Process | — | CMOS EPROM |
| I/O Standard | — | TTL/CMOS 5 V compatible |