EPM5192GI-1 vs EPM5192C-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GI-1 sa pamamagitan ng Altera at EPM5192C-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GI-1 | EPM5192C-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex Programmable Logic Device (CPLD) | Complex Programmable Logic Device (CPLD) |
| Architecture | PAL-type, UV-erasable CMOS | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Temperature na Operasyon | -40C to +85C (Industrial) | — |
| Packhaging | 84-pin PGA (Pin Grid Array), windowed ceramic | — |
| Configuration Memory | UV-EPROM (windowed ceramic PGA) | EEPROM (non-volatile) |
| Process Technology | CMOS | CMOS |
| Tindminan RoHS | unknown (legacy UV-windowed package) | unknown |
| External Clock Inputs | — | 1 |
| Propagation Delay (PIA, typical) | — | 45 ns |
| Maximum Operating Frequency | — | 50 MHz |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA) |
| Speed Grade | — | -2 |
| Programming Interface | — | JTAG / Altera MAX+ programming |
| Lead-Free | — | unknown |