EPM5192GI-1 vs EPM5192IC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GI-1 sa pamamagitan ng Altera at EPM5192IC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GI-1 | EPM5192IC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Architecture | PAL-type, UV-erasable CMOS | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (nominal 5 V) |
| Temperature na Operasyon | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Packhaging | 84-pin PGA (Pin Grid Array), windowed ceramic | 68-pin ceramic J-lead (IC-1 suffix) |
| Configuration Memory | UV-EPROM (windowed ceramic PGA) | — |
| Process Technology | CMOS | — |
| Tindminan RoHS | unknown (legacy UV-windowed package) | — |
| Usable Gates | — | 3750 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Technology | — | CMOS, UV-erasable, in-system programmable |
| Programming Interface | — | JTAG / IEEE Std 1149.1 boundary scan |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |