EPM5192GI-1 vs EPM5192IC-1 比較
詳細並排比較 EPM5192GI-1 由 Altera 與 EPM5192IC-1 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192GI-1 | EPM5192IC-1 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 EPLD |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Architecture | PAL-type, UV-erasable CMOS | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | 7 |
| Logic Array Blocks (LABs) | 12 | — |
| Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (nominal 5 V) |
| 工作溫度 | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| 封裝 | 84-pin PGA (Pin Grid Array), windowed ceramic | 68-pin ceramic J-lead (IC-1 suffix) |
| Configuration Memory | UV-EPROM (windowed ceramic PGA) | — |
| Process Technology | CMOS | — |
| RoHS 狀態 | unknown (legacy UV-windowed package) | — |
| Usable Gates | — | 3750 |
| I/O Pins | — | 64 |
| Pin-to-Pin Delay (tPD) | — | 15 ns (max, -1 speed grade) |
| Counter Frequency (fCNT) | — | 76.9 MHz |
| Technology | — | CMOS, UV-erasable, in-system programmable |
| Programming Interface | — | JTAG / IEEE Std 1149.1 boundary scan |
| Security Bit | — | Yes (design protection) |
| Supply Current (Icc, typical) | — | [DATA_NEEDED: Icc] mA |
| Output Drive Current (IOH/IOL) | — | [DATA_NEEDED: IOH/IOL] mA |