EPM5192GI-2 vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GI-2 sa pamamagitan ng Intel at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GI-2 | EPM5192JC-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Device Family | MAX 5000 | MAX 5000 |
| Product Type | UV-Erasable / OTP Complex PLD | UV-erasable Programmable Logic Device (PLD) |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Total Inputs | 72 | — |
| Propagation Delay (tPD) | 30 ns | 45 ns |
| Maksimum na Taktiko ng Oras | 33.3 MHz | 40 MHz |
| Supply Voltage (VCC) | 5 V nominal (4.5 V to 5.5 V) | — |
| Operating Temperature Grade | Industrial | — |
| Packhaging | 84-pin PGA (Pin Grid Array) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Package Code | PGA | — |
| Package Shape | Square | — |
| Terminal Form | PIN/PEG (through-hole) | — |
| Programming Method | UV-erase window (erasable) / OTP | UV-erase / EPROM |
| Process Technology | CMOS | CMOS |
| Tindminan RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS compliance] |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| External Clock Inputs | — | 1 |
| Uri ng Pagpapasok | — | Surface Mount |
| Number of Terminals | — | 84 |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |