EPM5192JC-1N vs EPM5192JC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1N sa pamamagitan ng Altera at EPM5192JC sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-1N | EPM5192JC |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates | 3750 | — |
| User I/O Pins | 64 | — |
| Dedicated Inputs | 7 | — |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | — |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Packhaging | 84-pin Ceramic Quad Flat Pack (CQFP) | 68-pin PLCC (JC) windowed ceramic |
| JEDEC Package Code | S-CQCC-J84 | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temperature range] | [DATA_NEEDED: commercial / industrial / military grade] |
| Programming Interface | JTAG / Altera ByteBlaster | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Uri ng Pagpapasok | — | Surface Mount |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | — | [DATA_NEEDED: tpd spec by speed grade] |
| Tindminan RoHS | — | [DATA_NEEDED: original Altera marking not RoHS] |