EPM5192JC-1N vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-1N sa pamamagitan ng Altera at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC-1N | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Usable Gates | 3750 | — |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| External Clock Inputs (GCLK) | 1 | — |
| Propagation Delay (tPD) | 40 ns | 45 ns |
| Maximum Clock Frequency (fMAX) | 62.5 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V | — |
| Technology | CMOS EPROM (UV-erasable) | — |
| Packhaging | 84-pin Ceramic Quad Flat Pack (CQFP) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| JEDEC Package Code | S-CQCC-J84 | — |
| Temperature na Operasyon | [DATA_NEEDED: industrial/commercial temperature range] | — |
| Programming Interface | JTAG / Altera ByteBlaster | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| External Clock Inputs | — | 1 |
| Maksimum na Taktiko ng Oras | — | 40 MHz |
| Process Technology | — | CMOS |
| Uri ng Pagpapasok | — | Surface Mount |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |
| Tindminan RoHS | — | [DATA_NEEDED: RoHS compliance] |