EPM5192JC-2 vs EPM5192JC-ES Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC-2 sa pamamagitan ng Altera at EPM5192JC-ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192JC-2 EPM5192JC-ES
Brand Altera Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 5000 MAX 5000
Product Type UV-erasable Programmable Logic Device (PLD) —
Macrocells 192 192
Logic Array Blocks (LABs) 12 12
Interconnect Programmable Interconnect Array (PIA) Programmable Interconnect Array (PIA)
User I/O Pins 64 [DATA_NEEDED: user I/O count for JC-ES in PLCC-84]
Dedicated Inputs 7 —
External Clock Inputs 1 —
Propagation Delay (tPD) 45 ns —
Maksimum na Taktiko ng Oras 40 MHz —
Process Technology CMOS —
Packhaging 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84)
Uri ng Pagpapasok Surface Mount Surface Mount
Number of Terminals 84 —
Programming Method UV-erase / EPROM —
Hanay ng Temperature na Operasyon [DATA_NEEDED: operating temperature range] —
Tindminan RoHS [DATA_NEEDED: RoHS compliance] [DATA_NEEDED: RoHS compliance]
Device Type — CPLD (EPLD)
Configuration Memory — EPROM (UV-erasable, one-time programmable for JC-ES)
Technology — CMOS
Programming — Altera MAX+PLUS II or compatible programmer
Temperature na Operasyon — [DATA_NEEDED: operating temperature range for ES grade]
Volte ng Pagbibigay — [DATA_NEEDED: VCC nominal]
Lead-Free — [DATA_NEEDED: lead-free status]
Level ng MSL — [DATA_NEEDED: MSL rating]
Note — Datasheet source: Altera MAX 5000 family document, 52 pages

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