EPM5192JC84-1 vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JC84-1 sa pamamagitan ng Altera at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JC84-1 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Type | UV-Erasable/OTP Complex Programmable Logic Device (CPLD) | — |
| Family | MAX 5000 | — |
| Macrocells | 192 | 192 |
| Propagation Delay (tpd) | 40 ns (worst case) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V ±5 %) | — |
| Process Technology | CMOS EPROM | CMOS |
| Operating Temperature Grade | Commercial | — |
| Packhaging | 84-terminal Ceramic Chip Carrier (CQCC84 / J-lead) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| JESD-30 Package Code | S-CQCC-J84 | — |
| Terminal Form | J-BEND | — |
| Package Shape | SQUARE | — |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Programmability | UV-erasable (window) / OTP in production | — |
| Configuration Memory | EPROM (non-volatile, instant-on) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| User I/O Pins | — | 64 |
| Dedicated Inputs | — | 7 |
| External Clock Inputs | — | 1 |
| Propagation Delay (tPD) | — | 45 ns |
| Maksimum na Taktiko ng Oras | — | 40 MHz |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |