EPM5192JI-1 vs EPM5192JC-2 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192JI-1 sa pamamagitan ng Intel at EPM5192JC-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192JI-1 | EPM5192JC-2 |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CMOS UV-Erasable Programmable Logic Device (PLD / EPLD) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Propagation Delay (tPD) | 55 ns | 45 ns |
| Supply Voltage (VCC) | 4.5 V to 5.5 V (nominal 5 V) | — |
| Process Technology | CMOS EPROM | CMOS |
| Packhaging | 84-pin JLCC (Windowed ceramic J-lead) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Temperature na Operasyon | Industrial, -40 C to +85 C | — |
| Configuration Memory | UV-erasable EPROM | — |
| Programming Method | External EPROM programmer (via programming hardware) | UV-erase / EPROM |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Speed Grade | -1 (slowest grade in EPM5192 family) | — |
| Logic Element per Macrocell | 1 D flip-flop + AND/OR array | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| External Clock Inputs | — | 1 |
| Maksimum na Taktiko ng Oras | — | 40 MHz |
| Uri ng Pagpapasok | — | Surface Mount |
| Number of Terminals | — | 84 |
| Hanay ng Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range] |