EPM5192LC-35 vs EPM5192JC-1 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-35 sa pamamagitan ng Altera at EPM5192JC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-35 EPM5192JC-1
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Series MAX 5000 —
Family MAX 5000 CPLD MAX 5000
Logic Elements / Macrocells 192 macrocells —
Pin-to-Pin Delay (tPD) 35 ns —
Speed Grade -35 —
Programmable Type UV-Erasable / OTP (EPROM-based) —
Package Type JLCC (J-Lead Ceramic Chip Carrier) 84-pin Ceramic Quad Flat Pack (CQFP), windowed
Uri ng Pagpapasok Surface Mount —
Logic Voltage 5 V TTL-compatible I/O —
Temperature na Operasyon Commercial (0C to +70C) per LC suffix 0 C to +70 C (commercial)
Programming Method Altera legacy programmer (EPROM-based) —
Architecture LAB-based with Programmable Interconnect Array (PIA) —
I/O Standard TTL TTL/CMOS 5 V compatible
Tindminan RoHS Non-compliant (ceramic hermetic package) —
Katayuan ng Lifecycle Obsolete - last-time-buy stock only —
Datasheet Document Altera MAX 5000 family datasheet (per alldatasheet.com) —
Device Type — CPLD - Complex Programmable Logic Device
Technology — CMOS, UV-Erasable / OTP
Macrocells — 192
Usable Gates — 3750
Propagation Delay (tPD) — 40 ns (speed grade -1)
Maximum Internal Frequency (fMAX) — 62.5 MHz
Supply Voltage (VCC) — 4.75 V to 5.25 V
User I/O Pins — 84
JEDEC Package Code — S-CQCC-J84
Configuration Memory — UV-EPROM (erasable under UV lamp)
Programming Interface — Altera MAX programming interface (parallel, pre-JTAG for this family)
Process — CMOS EPROM

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