EPM5192LC-M091A vs EPM5192LC Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-M091A sa pamamagitan ng Altera at EPM5192LC sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC-M091A | EPM5192LC |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Device Family | MAX 5000 EPLD | — |
| Macrocells | 192 | 192 |
| User I/O Pins | 64 | 64 |
| Dedicated Inputs | 7 | 7 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Global Clock Inputs | 1 | 1 |
| Propagation Delay (tpd) | 55 ns (typical, MAX 5000 family) | — |
| Supply Voltage (Vcc) | 5 V | — |
| Technology | UV-erasable CMOS, EPROM-based | — |
| Interconnect | Programmable Interconnect Array (PIA) | — |
| Packhaging | LC (custom pin-grid / customer-specific, M091A designation) | JLCC-68 (windowed ceramic, LC suffix) |
| Bilang ng Pin | [DATA_NEEDED: pin count of LC-M091A package] | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | — |
| Configuration Memory | Non-volatile EPROM (UV-erasable) | — |
| Development Tool | Altera MAX+PLUS II (legacy) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status for EPM5192LC-M091A] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 7000S |
| Propagation Delay (tPD) | — | 55 ns (typical, commercial) |
| Maximum Clock Frequency (fMAX) | — | 50 MHz |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (nominal 5 V) |
| Process Technology | — | CMOS, UV-erasable/OTP EPROM configuration |
| Programmable Interconnect | — | Programmable Interconnect Array (PIA), fixed delay |
| Boundary-Scan Support | — | JTAG IEEE 1149.1 |
| Programming Interface | — | JTAG (ByteBlaster-compatible) |
| Operating Temperature (commercial) | — | 0C to +70C |
| Uri ng Pagpapasok | — | Surface Mount |