EPM5192LC-M205A vs EPM5192GC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-M205A sa pamamagitan ng Altera at EPM5192GC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC-M205A | EPM5192GC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | NRND | Obsolete |
| Family | MAX 5000 | MAX 5000 (Classic) |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| Dedicated Inputs | 7 | 7 |
| I/O Pins | 64 | — |
| Propagation Delay (tPD) | 55 ns | — |
| Supply Voltage (VCC) | 5 V | 4.75 V to 5.25 V |
| Technology | CMOS EPROM (UV-erasable / OTP) | — |
| Programmable Interconnect | Programmable Interconnect Array (PIA) | — |
| Global Clock Inputs | 1 | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | [DATA_NEEDED: operating temperature grade] |
| Package Type | 205-pin (M205A) | — |
| Uri ng Pagpapasok | Surface Mount | Through-Hole (PGA) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS status] |
| Configuration Memory | UV-erasable / OTP EPROM | — |
| Logic Type | — | CPLD (Complex Programmable Logic Device) |
| Usable Gates | — | 3,750 |
| User I/O Pins | — | 64 |
| Maximum Propagation Delay (tPD) | — | 40 ns |
| Maximum Frequency (fMAX) | — | 62.5 MHz |
| Process Technology | — | CMOS, UV-erasable / OTP |
| Packhaging | — | 100-pin Ceramic PGA (GC) |
| Configuration Method | — | UV-Erase / One-Time Programmable |
| Interconnect | — | Peripheral Interconnect Array (PIA) |