EPM5192LC1 vs EPM5192LC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC1 sa pamamagitan ng Altera at EPM5192LC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192LC1 | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | EPLD / CPLD |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | — |
| Dedicated Inputs | 7 | 7 |
| User I/O Pins | 64 | — |
| Packhaging | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | — |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Supply Voltage Range | 4.75 V to 5.25 V | — |
| Maksimum na Taktiko ng Oras | 50 MHz | 50 MHz |
| Propagation Delay (tPD) | 40 ns | — |
| Process Technology | CMOS EPROM | — |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | — |
| Operating Temperature (Commercial 'LC') | 0 °C to 70 °C | — |
| Uri ng Pagpapasok | Surface Mount | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| JEDEC Package Code | S-PQCC-J84 | — |
| Logic Gates | — | 3750 (typical usable) |
| User I/O | — | 64 |
| Bilang ng Pins | — | 84 |
| Package Type | — | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Propagation Delay | — | 25 ns |
| Volte ng Pagbibigay | — | 5 V nominal (4.75 V to 5.25 V) |
| Technology | — | CMOS, UV-erasable / OTP EPROM cell |
| Temperature na Operasyon | — | 0C to +70C (commercial) |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |
| Speed Grade | — | -1 |