EPM5192LI-1 vs EPM5192LI-2 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LI-1 sa pamamagitan ng Altera at EPM5192LI-2 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LI-1 EPM5192LI-2
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle NRND Obsolete
Family MAX 5000 MAX 5000
Device Type EPLD (UV-Erasable/OTP Complex PLD) EPLD (Erasable/OTP Complex PLD)
Usable Gates 3,750 —
Macrocells 192 192
Maximum Toggle Frequency 40 MHz —
Volte ng Pagbibigay 5 V 4.5 V to 5.5 V
Propagation Delay (tPD) [DATA_NEEDED: tPD in ns at -1 grade] —
User I/O Pins [DATA_NEEDED: user I/O count for JLCC variant] —
Package Type JLCC (windowed, ceramic, UV-erasable) —
Process Technology CMOS EPROM, UV-erasable —
Speed Grade -1 —
Temperature na Operasyon [DATA_NEEDED: industrial vs military range] -40 C to +85 C (industrial)
Bilang ng Pin [DATA_NEEDED: pin count of LI package] —
Uri ng Pagpapasok Surface Mount (JLCC with J-leads) Surface Mount
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status of ceramic LI variant] [DATA_NEEDED: RoHS status]
Lead Free [DATA_NEEDED: lead-free] —
Programmable Interconnect Programmable Interconnect Array (PIA) —
Architecture EEPROM/EPROM-based, non-volatile, instant-on —
Logic Array Blocks (LABs) — 12
User I/O — 64
Total Inputs — 72 (7 dedicated + 64 I/O)
Propagation Delay (tpd) — 55 ns (max)
Maximum Internal Frequency — 100 MHz
Typical Power Dissipation — 600 mW at 5 V / 25 C
Technology — CMOS, UV-erasable / OTP
Packhaging — 84-pin PLCC (J-lead), JEDEC S-PQCC-J84
Design Toolchain — Altera MAX+plus II

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