EPM570F100C4N vs EPM570F100A5N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM570F100C4N sa pamamagitan ng Intel at EPM570F100A5N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM570F100C4N | EPM570F100A5N |
|---|---|---|
| Brand | Intel | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Aktibo | Aktibo |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 440 LE | 570 |
| Macrocells | 440 | 440 |
| Maximum User I/O | 80 | — |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | — |
| User Flash Memory | 4.4 Kbits | 8 Kbits |
| Configuration Technology | Flash (non-volatile, instant-on) | — |
| Operating Voltage (Core) | 3.3 V (internal regulator) | — |
| I/O Voltage Support (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| Packhaging | 100-FBGA (FineLine BGA) 11 mm x 11 mm | 100-ball FBGA |
| Temperature na Operasyon | 0 C to +85 C (commercial) | 0°C to +85°C (commercial) |
| Uri ng Pagpapasok | Surface Mount (BGA) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Hot Socketing | Yes | — |
| Pin-to-Pin Delay (tPD) | — | 5.4 ns |
| Maximum Operating Frequency | — | 201.1 MHz |
| User I/O Pins (max) | — | 76 |
| Global Clock Lines | — | 4 |
| Supply Voltage - Core | — | 3.3 V |
| Supply Voltage - I/O Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Process Technology | — | 0.18 µm flash |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| Tindminan RoHS | — | Compliant |