EPM570F100C4N vs EPM570F100A5N 比較
詳細並排比較 EPM570F100C4N 由 Intel 與 EPM570F100A5N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM570F100C4N | EPM570F100A5N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | 啟用中 | 啟用中 |
| Family | MAX II | MAX II |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Elements | 440 LE | 570 |
| Macrocells | 440 | 440 |
| Maximum User I/O | 80 | — |
| Pin-to-Pin Delay (tPD1) | 5.4 ns | — |
| User Flash Memory | 4.4 Kbits | 8 Kbits |
| Configuration Technology | Flash (non-volatile, instant-on) | — |
| Operating Voltage (Core) | 3.3 V (internal regulator) | — |
| I/O Voltage Support (VCCIO) | 1.5 V / 1.8 V / 2.5 V / 3.3 V | — |
| 封裝 | 100-FBGA (FineLine BGA) 11 mm x 11 mm | 100-ball FBGA |
| 工作溫度 | 0 C to +85 C (commercial) | 0°C to +85°C (commercial) |
| 安裝類型 | Surface Mount (BGA) | — |
| JTAG Support | Yes (IEEE 1149.1 boundary-scan) | — |
| Hot Socketing | Yes | — |
| Pin-to-Pin Delay (tPD) | — | 5.4 ns |
| Maximum Operating Frequency | — | 201.1 MHz |
| User I/O Pins (max) | — | 76 |
| Global Clock Lines | — | 4 |
| Supply Voltage - Core | — | 3.3 V |
| Supply Voltage - I/O Banks | — | 1.5 V / 1.8 V / 2.5 V / 3.3 V |
| Process Technology | — | 0.18 µm flash |
| Programming Interface | — | JTAG (IEEE 1149.1) / ISP |
| RoHS 狀態 | — | Compliant |